The non-provisional patent application aims to protect methods and systems to automatically generate reusable layout block IPs of microchips

SAN DIEGO, Oct. 6, 2022 (GLOBE NEWSWIRE) — GBT Technologies Inc. (OTC PINK: GTCH) (“GBT” or the “Company”), filed a non-provisional patent application to protect an Electronic Design Automation (EDA) software technology, internally codenamed Phi, whose software is used to automate the generation of reusable integrated circuit (IC) layout blocks . The concept creates a layout according to the IC specification and aims to save time when designing a microchip. The IP block can be used as a black box that can be inserted into existing or future IC projects as a plug and play unit with the aim of saving time by avoiding a complete redesign process. The patent was filed on September 27, 2022 and was assigned an application ID: 17953378. Intellectual property (IP) related to semiconductors is a reusable logic or layout unit design that is developed with the intention of being licensed to multiple vendors or shared internally use as building blocks in various chip designs. Using reusable IPs is an efficient way to quickly design a System-on-Chip (SoC). A SoC is an IC that contains the components of sub-units. It typically consists of core blocks, each with its own task, such as: such as internal memory, central processing unit (CPU), input/output ports, and more. Modern SoCs can also contain AI and other complex blocks to enable advanced functionality. The use of reusable, pre-engineered IP cores/blocks is becoming increasingly important to minimize overall IC design time. The non-provisional patent application describes a system that aims to generate IC layout IP blocks automatically, with a defined process reading design rules, constraints and the microchip’s specifications. The goal of this IP is to reduce the design and cost of IC project and silicon space…